1. Field of the Invention
This invention generally relates to a ball grid array (BGA) package, and more particularly to a BGA package using a wire bonding technique.
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the speed and the complexity of the IC chip have increased. Accordingly, a need has arisen for higher package efficiency. To meet the need, the ball grid array (BGA) technology has been developed by the semiconductor industry.
Although the conductive traces pads on a BGA substrate can be lithographically defined to achieve a very fine pitch, the bond pad pitch on the semiconductor die is typically restricted from achieving a comparable pitch due to spacing and design rules used to account for wire bonding methods and tolerances, such as capillary tool interference during wire bonding.
Conventional IC bond pad designs include (a) single in-line bond pad design and (b) staggered bond pad design. Typically, the number of connections to external circuit elements, commonly referred to as "input-output" or "I/O" connections, is determined by the structure and function of the chip. Advanced chips capable of performing numerous functions may require a substantial number of I/O connections. For high I/O count IC chips, the staggered bond pad design has been used so as to increase the maximum allowable pad number that can be designed on a chip. This has the benefit of providing not only more bonding pads per chip, but also shorter metal wires and thus faster circuits.
FIG. 1 shows a conventional plastic BGA package 100 comprising a chip 110 with a staggered bond pad design disposed on the upper surface of a substrate 120. The chip 110 and a portion of the upper surface of the substrate 120 are encapsulated in a package body 150. The upper surface of the substrate 120 is provided with a ground ring 122, a power ring 124, and a plurality of conductive traces 126 (see FIG. 2). The active surface of the chip 110 is provided with a plurality of the bonding pads 112 positioned in two rows. The bonding pads 112 on the chip 110 typically include power pads, ground pads and I/O pads. The power pads are used for supplying the source voltage. The ground pads are used for supplying the ground potential.
Typically, the number of the I/O pads accounts for about two-thirds of the total number of the bonding pads 112. Thus, at least some of the outer row of bonding pads 112 must be designed as I/O pads. The outer row of bonding pads 112 is referred to as bonding pads closest to the sides of the chip. Therefore, at least four tiers of bonding wires with different loop heights are required for avoiding short circuiting, wherein the bonding wires electrically connect the chip 110 to the substrate 120. The first tier bonding wires 112a (lowest loop height) connect the ground pads designed in the outer row of the bonding pads to the ground ring 122 of the substrate 120. The second tier bonding wires 112b connect the power pads designed in the outer row of the bonding pads to the power ring 124 of the substrate 120. The third tier bonding wires 112c connect the I/O pads designed in the outer row of the bonding pads to corresponding conductive traces 126 of the substrate 120. The fourth tier bonding wires 112d connect the I/O pads designed in the inner row of the bonding pads to corresponding conductive traces 126 of the substrate 120. The wire bonding parameters of each tier must be optimized separately. Therefore, the four tiers of bonding wires 112a, 112b, 112c, 112d require at least four times of wire bonding operations. Difficulty and risks of wire bonding are proportional to the number of wire bonding operations required.
It has been revealed that using an array of pads instead of using only perimeter pads can increase the maximum allowable pad number that can be designed on a chip. However, this will greatly increase the difficulty of wire bonding as described above.